SSDs are about to get a whole lot bigger and a whole lot cheaper. Intel and Micron on Monday afternoon announced the delivery of the industry’s first Quad-Level Cell NAND dies, which will offer a third more space than previous technology.
QLC technology stores four bits per cell on a NAND cell, which is a significant increase over today’s common TLC (Triple-Level Cell) NAND.
Why this matters: As users hunger for ever more storage capacity, SSD makers have labored to add additional layers to meet those demands. QLC will give the title of densest flash to Micron and Intel with a single die capable of holding 1 terabit of information, the companies said.
SSD capacity has grown gradually. The first SSDs used Single-Level Cell and stored a single-bit per cell. That moved to two-bits per cell with Multi-Level Cell, and to 3-bits per cell with Triple-Level Cell technology. With QLC, Intel and Micron have achieved the next step.
“With introduction of 64-layer 4bits/cell NAND technology, we are achieving 33 percent higher array density compared to TLC, which enables us to produce the first commercially available 1 terabit die in the history of semiconductors,” said Micron Executive Vice President, Technology Development, Scott DeBoer. “We’re continuing flash technology innovation with our 96-layer structure, condensing even more data into smaller spaces, unlocking the possibilities of workload capability and application construction.”
Intel, which has had a joint R&D effort with Micron, also chimed in about the technological impact. “Commercialization of 1Tb 4bits/cell is a big milestone in NVM history and is made possible by numerous innovations in technology and design that further extend the capability of our Floating Gate 3D NAND technology,” said RV Giridhar, Intel vice president, Non-Volatile Memory Technology Development. “The move to 4bits/cell enables compelling new operating points for density and cost in Datacenter and Client storage.”
Besides the QLC breakthrough, Intel and Micron executives also announced a third-generation 3D NAND that should provide a 50-percent increase in layers. Execs from the companies said both technologies use CMOS under the Array (CuA) to reduce die size and increase performance.
Neither company said which customers had received the dies, nor when consumers would be able to buy them. More importantly: No price was announced. Because the TLC NAND it’s targeting usually plays in the budget storage arena, we’d expect it to drastically rejigger the cost of SSDs once it’s out.